Advances in High Performance Computing by Ashutosh Tiwary, Janusz Kowalik, Bob Abarbanel, John Lixvar,

By Ashutosh Tiwary, Janusz Kowalik, Bob Abarbanel, John Lixvar, Vish Jumani (auth.), Lucio Grandinetti, Janusz Kowalik, Marian Vajtersic (eds.)

Most of the papers during this quantity have been awarded on the NATO complicated examine Workshop excessive functionality Computing: know-how and alertness, held in Cetraro, Italy from 24 to 26 of June, 1996. the most goal of the Workshop used to be to debate a few key clinical and technological advancements in excessive functionality computing, determine major tendencies and defme fascinating study targets. the quantity constitution corresponds, quite often, to the description of the workshop technical time table: common strategies and rising platforms, software program expertise, algorithms and purposes. one of many Workshop suggestions was once an attempt to increase a bit of the scope of the assembly from scientific/engineering computing to enterprise-wide computing. The papers on functionality and scalability of database servers, and Oracle DBMS mirror this try we are hoping that when examining this choice of papers the readers can have a good suggestion approximately a few very important examine and technological concerns in excessive functionality computing. we want to provide our due to the NATO medical and Environmental Affairs department for being the crucial sponsor for the Workshop. additionally we're happy to recognize different associations and corporations that supported the Workshop: ecu Union: ecu fee DGIII-Industry, CNR: nationwide examine Council of Italy, college of Calabria, Alenia Spazio, Centro Italiano Ricerche Aerospaziali, ENEA: Italian nationwide company for brand spanking new expertise, power and the surroundings, Fujitsu, Hewlett Packard-Convex, Hitachi, NEC, Oracle, and Silicon Graphics-Cray learn. Editors January 1997 vii record OF participants Ecole Nonnale Su¢rieure de Lyon, 69364 Abarbanel. Robert M.

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This read-only workload with little coherence traffic can fit well within a SMP node; this reduces remote references and increases scalability. This conclusion is supported by very low number of remote references observed in simulated TPC-D workloads on a NUMA machine [2]. Since the underlying NUMA hardware is similar to MPP systems, we also expect the system hardware to scale well for such workloads, particularly because the high-overhead DSM components of the NUMA system are not being heavily utilized.

This paper discusses the scalable shared memory multiprocessor (SSMP), which removes the drawbacks of the traditional SMP systems. The first part of this paper reviews current parallel processing alternatives, and introduces the scalable SMP architecture. The second part of the paper focuses on a particular instance of a scalable SMP, the Silicon Graphics Origin multiprocessor and its S2MP memory architecture. We give an overview of the Origin system and then discuss some of the important design trade-oft's in the architecture and implementation of the system.

I . [ . . a.. _. •····-· . -......... ......................... 1 1 . 1 ~--------~--------~--------~--------~ 1993 1994 1995 1996 1997 Figure 2: The performance over time normalized by the average performance of the systems in the Top500. 31 Digital Alpha Server. These systems entered the list in late 1994 and during 1995 in quite impressive numbers [7]. Position 100 showed a similar increase until 1995, indicating that the majority of installations was happening past this position. During 1996 the curve for position 100 start to drop down.

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