Computing with Memory for Energy-Efficient Robust Systems by Somnath Paul

By Somnath Paul

This ebook analyzes power and reliability as significant demanding situations confronted via designers of computing frameworks within the nanometer expertise regime. The authors describe the prevailing ideas to handle those demanding situations after which show a brand new reconfigurable computing platform, which leverages high-density nanoscale reminiscence for either facts garage and computation to maximise the energy-efficiency and reliability. The power and reliability merits of this new paradigm are illustrated and the layout demanding situations are mentioned. a variety of and software program features of this fascinating computing paradigm are defined, rather with appreciate to hardware-software co-designed frameworks, the place the unit should be reconfigured to imitate diversified software habit. ultimately, the energy-efficiency of the paradigm defined is in comparison with different, recognized reconfigurable computing platforms.

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MBC has the following differences with the spatio-temporal frameworks proposed till date: 1. As opposed to [9–11], MBC is a fine-grained reconfigurable framework. In contrast to [9–11] which incorporate an ALU for multi-cycle execution, in the MBC framework, multi-input multi-output LUTs representing the input application are mapped to a dense 2-D memory array for the purpose of temporal computing. 2. Interconnect is statically scheduled in case of MBC. Hence, MBC poses unique placement and routing challenges, different from those addressed in [12].

S. Golshan, E. Bozorgzadeh, “Single-Event-Upset (SEU) Awareness in FPGA Routing”, in DAC, 2007 Chapter 3 Motivation for a Memory-Based Computing Hardware Abstract In this chapter we first provide a summary of the desired characteristics that a compute framework must have to overcome the challenges faced by conventional hardware and software reconfigurable frameworks at nanoscale technologies. We then provide an outline for a new computing model which bridges the gap between memory and logic. Given the rapid evolution of CMOS and non-CMOS memory technologies, we explain the benefits of such in-memory computing model.

MATRIX: As shown in Fig. 5a is a coarse-grained reconfigurable array which supports configurable instruction distribution. MATRIX is an improvement over the DPGA concept. Rather than separate the resources for instruction storage and distribution from the resources for data storage and computation and dedicate silicon resources to them at fabrication time, the MATRIX architecture unifies these resources. Once unified, traditional instruction and control resources are decomposed along with computing resources and can be deployed in an application-specific manner.

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